Semiconductor integrated circuits with high device density require the patterning of closely spaced submicrometer lines in semiconductors materials to form submicron geometries such as small area emitters for bipolar transistors, short gates for field effect transistors and narrow interconnection lines between devices. The formation of such polysilicon, metal or insulator structures typically requires definition of the locations of such structures in a layer of photoresist, which in turn is formed on a layer of conductor or insulator to be etched. The definition of the location of such structures is accomplished by exposing the photoresist to light passing through a reticle or photomask which contains the desired pattern. After exposure and treatment of the photoresist, the underlying layer is plasma etched using the patterned photoresist as a template. Subsequent processing steps are determined according to the type of device to be fabricated.
As advances in photolithographic and processing capabilities progressively increase, the lateral dimensions of features in silicon integrated circuits continue to decrease. Fabrication of reduced device geometries in integrated circuits mandates minute contact holes of submicron size within insulation layers and minimum isolation distance requirements measured in terms of critical dimensions (CD). For example, recent generations of complementary metal-oxide silicon integrated circuits (CMOS) have gate regions with dimensions on the order of 0.25 microns, and will have dimensions on the order of 0.18 microns and less in the near future.
During photolithography, problems arise because high resolution submicrometer images in photoresist require shallow depth of focus during exposure, but thick photoresist patterns are required because of the poor etch rate between the photoresist and the underlying semiconductor layer. During this process, the substrate is exposed to ion and electron bombardment, UV light, X-rays, and scattered radiations. As a consequence, irregular topographies, distorted images, large striations and uncontrolled increases in the size of the contact openings or holes, known as CD losses, occur during the exposure of the photoresist layer.
Irregular topographies and CD loss also occur as a result of the plasma etch attacking the side walls of the contact opening. When two discontinuities are formed in adjacent contact openings, the integrated circuit suffers a loss in critical dimension (CD loss), which is critical especially in the sub-quarter micron regime. As a result of the irregular contact openings, an unwanted and uncontrolled increase in the diameter of the contact openings may also result. This increased size also impacts the displacement of the metal atoms that fill the contact openings. Thus, in addition to the loss in critical dimension, electrical contacts may also become unreliable.
Accordingly, there is a need for an improved method of forming contact openings without a reduction in the critical dimension and without striations formed in the sidewalls of such contact openings. There is further a need for an improved method of forming contact openings which employs fewer and simpler processing steps.